1. Field of the Invention
The present invention relates in general to the compensation for a motion of a high definition video, and more particularly to a video motion compensation apparatus in which read and write operations of frame memories are processed in parallel at divided eight phases, so that a large amount of data can be processed in real time.
2. Description of the Prior Art
Video motion compensation is for reproducing video data compressed and transmitted to a decoder stage to a better picture quality using a motion vector detected at an encoder stage. For such video motion compensation, there are conventionally employed two frame memories. Video data is read from a location of the first frame memory corresponding to an address varied by a motion amount from a location of a macro block of 16.times.16 pixels. The read video data from the first frame memory is added to input video data and then written into the second frame memory.
Referring to FIG. 1, there is shown a block diagram of a conventional video motion compensation apparatus. As shown in this drawing, the conventional video motion compensation apparatus comprises an address generator 11 for generating read and write addresses of frame memories 13 and 14 in response to a macro block address MBA designating an X-location of a macro block, a macro slice address MSA designating a Y-location of the macro block and a motion vector (X,Y) and outputting the generated read and write addresses to an address controller 12.
The address controller 12 is adapted to apply the read and write addresses from the address generator 11 to the frame memories 13 and 14 and output a control signal to a data input/output (I/O) controller 15.
The data I/O controller 15 is operated in response to the control signal from the address controller 12 to select one of the frame memories 13 and 14 in a data read operation and the other frame memory 13 or 14 in a data write operation.
Each of the frame memories 14 and 15 is operated under the control of the data I/O controller 15 to output video data stored in its location corresponding to the read address from the address controller 12 to an adder 16 and store video data from the adder 16 in its location corresponding to the write address from the address controller 12.
The adder 16 is adapted to add the video data from one of the frame memories 13 and 14 to inverse discrete cosine transform (IDCT) video data and output the resultant video data to the other frame memory 13 or 14.
A clock generator 10 is also provided in the conventional video motion compensation apparatus to count input clocks to generate a clock signal.
The operation of the conventional video motion compensation apparatus with the above-mentioned construction will hereinafter be described.
The macro block address MBA designating the X-location of the macro block, the macro slice address MSA designating the Y-location of the macro block and the motion vector (X,Y) are applied from an encoder (not shown) to the address generator 11. Then, the address generator 11 generates the read and write addresses of the frame memories 13 and 14 in response to the clock signal from the clock generator 10. As a result, video data of the macro block is read from the location of one of the frame memories 13 and 14 corresponding to the read address from the address generator 11. Also, video data the motion of which is compensated for by the motion vector from the location of the macro block is written into the location of the other frame memory 13 or 14 corresponding to the write address from the address generator 11. The read and write addresses from the address generator 11 are applied to the address controller 12.
The address controller 12 applies the read and write addresses from the address generator 11 to the frame memories 13 and 14 and outputs the control signal to the data I/O controller 15. In response to the control signal from the address controller 12, the data I/O controller 15 selects one of the frame memories 13 and 14 so that the video data can be read from the location of the selected memory 13 or 14 corresponding to the read address from the address controller 12. The read video data from the frame memory 13 or 14 is applied to the adder 16, which then adds the read video data to the IDCT video data. The resultant video data from the adder 16 is written into the location of the other frame memory 13 or 14, which is selected by the data I/O controller 15 under the control of the address controller 12, corresponding to the write address from the address controller 12.
The above-mentioned conventional video motion compensation apparatus must have a data processing speed of 60MHz or more to process a large amount of data in real time. In this connection, the conventional video motion compensation apparatus has the disadvantage that it is difficult to select components applicable to such a high frequency. Also, the use of such a high frequency makes the system unstable. Further, the use of an erasable programmable logic device (EPLD), being widely used now, is suppressed due to the limits of the frequency.